The success of CMOS has overshadowed nearly all other solid-state device innovations over recent decades. With fundamental CMOS scaling limits close in sight, the time is now ripe to explore disruptive computing technologies. As a viable post-CMOS computing technology, superconductor electronics can deliver ultra-high performance and energy efficiency at scale, thereby paving the way for seminal innovations in integrated electronics, sustainable exascale computing, and acceleration of machine learning. This half-day workshop will cover the challenges and opportunities associated with the first-time design of a superconductive system of cryogenic computing cores (SuperSoCC), which is the focus of a recently awarded NSF Expeditions in Computing award. To demonstrate SuperSoCC, a slew of challenges related to physical scaling, chip-level integration, compact modeling and design tool support, on-chip memory design, architecture design, and full-system design and integration including interfacing to room temperature electronics must be addressed. These issues will be addressed through a series of talks given by experts in the field.


Massoud Pedram: DISCoVER Expedition Overview

Eby Friedman: Design Methodologies and Circuits for Superconductive Systems

Murali Annavaram: Architectural Implications of Superconductive Electronics

Nobuyuki Yoshikawa and Chris Ayala: Energy-Efficient Superconductive Integrated Circuits based on Adiabatic Quantum Flux Parametron: Toward Large-Scale and High-Dence Integration

Scott Holmes: Back-of-the-Envelop Calculated Roadmap Guidance for Superconductor Electronics

Michael Hamilton: Interconnects and Devices for Superconductive Systems

Oleg Mukhanov and Ivan Nevirkovetz: High-Density Memory Based on Stacked Magnetic and Josephson Junctions

Yanzhi Wang: Design Automation and Ultra-Energy Efficient Deep Learning Framework using AQFP Superconducting Technology