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This talk will begin with a brief overview of superconducting digital logic and the physical realization of superconducting qubits. After reviewing key operating principles, the focus will shift to the interface circuits that connect superconducting digital controllers to qubit and readout subsystems.

This talk presents recent advances in RQL-based qubit control circuits, with a focus on dual-rail qubit architecture and how controlled entanglement operations can be implemented in a cryogenic digital environment. Slides available for download.

Overview of the SuperSoCC architecture — integrating SFQ compute cores, cryogenic SRAM, and DRAM at different temperature tiers. This talk covers the memory subsystem design and the challenges of room-temperature I/O interfacing.

This talk reviews the current state of AQFP (Adiabatic Quantum Flux Parametron) logic, discussing the energy efficiency limits achievable with current Nb fabrication processes and progress toward higher junction-count circuits for general-purpose compute.

Covers the niobium trilayer fabrication process used across DISCoVER partner institutions, with a focus on junction uniformity across wafers and its implications for large-scale SFQ circuit yield. Includes live demo of test-chip measurement data.

Presents the design methodology developed for distributing bias currents across large ERSFQ circuits without static power loss. This talk accompanies the paper published in IEEE Transactions on VLSI Systems (Vol. 28, No. 11, 2020).

Introduces the α-Soma cell — a single flux quantum threshold gate designed to implement spiking neural network operations at cryogenic temperatures. The design achieves sub-picojoule switching energy per synaptic event.