Design tools, standard-cell libraries, and datasets developed by the DISCoVER Expeditino team, made available so companies and researchers outside the collaboration can build on the same foundation.
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A Superconducting Hybrid SpikingOscillatory Neural Network Using State-Reconfigurable Flux Oscillator
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what it was developed for, and how researchers or
companies might use it.
License: [TBD] · Version: [TBD]
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AC-Biased Bistable Vor- tex Memory Using -Junctions for Scalable Superconducting Memory Arrays
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Clock Distribution Networks for Serial Biasing of SFQ Circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Compact AC Power Delivery Method for RSFQ and FPL
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Comparison of EM simulation-based RLGC extraction and an- alytic RLGC models for superconducting transmission lines
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Dynamic Single Flux Quantum Half-Adder
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Epitaxial growth of δ -NbN on MgO(001) by PAMBE
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
High-performance Cryo-CMOS SRAM array for SFQ circuits (Product 8)
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Icy-Hot: Decoupled Compute Paradigm to- wards a General-Purpose Superconducting CPU Design
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Modelling of Multi-Photon Events of a Super- conducting Single-Photon Nanostripe Detector for Photon Number Resolution Experiments
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Lightweight error-correction code encoders in superconducting elec- tronic systems
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Operating Margin and Robustness of AC-Biased Superconductive Logic Under Non-Ideal Bias Distribution
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Photon-Number-Resolving Readout for a Large-Area Superconductor Nanostripe Single-Photon Detector
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Post-Placement Timing Closure for AQFP Circuits via MaxMin Clock Margin Optimization
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Scalable Superconducting Neural Network: A Bit-Parallel Approach using RQL-RSFQ Hybrid Logic
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Simulation and optimization of SFQ interface circuit operating margins for data link (Product 16)
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Spiking-Hopfield Neural Networks with SFQ Logic
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Superconducting Echo State Network for High-Speed SQUID Readout
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Superconductor Systolic Array Implementation with Novel Trans- mission Gate
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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AC Biased SFQ Clock Splitters for Current Mitigation
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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AC Power Delivery for Fast Phase Logic
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
An On-Chip Control and Readout Circuit Design for an Ising Annealer
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Characteristics of Nb-Based Josephson Junctions With TaNx and TaNx/(Pd-Ni) Barriers
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Compact Model and Circuit Behavior of Bistable 2ϕ-Josephson Junctions (Product 24)
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Current Recycling in Heterogeneous RSFQ Circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Design Guidelines for Superconducting Digital Circuits Employing π-JJs with Ferromagnetic Barriers
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Epitaxial Growth and Phase Stabilization of δ-NbN on MgO by PAMBE
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Fabrication and Characteristics of Self-Shunted Nb/TaNx/Nb Josephson Junctions
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Icy-Hot: Decoupled Compute Paradigm Towards a General-Purpose Superconducting CPU Design
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Inductorless Dynamic Logic Based on 2ϕ-Josephson Junctions (Product 30)
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Josephson Junctions with Ferromagnetic Barriers for Digital Superconducting Electronics: A Review
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Multi-Input SFQ Multiplexers
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Optimized bistable vortex memory arrays for superconducting in-memory matrix-vector multiplication
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Programmable Bistable Vortex Logic for Scalable Superconductor Electronics
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Reed-Muller error-correction code encoder for SFQ-to-CMOS interface circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Scalable Asynchronous Single Flux Quantum Up-Down Counter Using Josephson Trapping Lines and α-Cells
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Scalable superconducting neuron with ternary synaptic connections for ultra-fast SNN hardware
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Signal integrity simulations of 4JL gate pulses from 4 K to 50 K
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Single Source SFQ Multiclock Generator using Resistor-JTL Branches
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Superconductor bistable vortex memory for data storage and readout
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
SuperSNN: A Hardware-Aware Framework for Physically Realizable, High-Performance Superconducting Spiking Neural Network Chips
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
System-level comparison of superconductor-semiconductor interface circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Ternary digital output data link from SFQ circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Electrical Characteristics of Serially Biased ERSFQ Circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Inductorless Fast Phase Logic: Enabling Two-Order-of-Magnitude Density Scaling for Superconductor VLSI
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Interfacing superconductor and semiconductor digital electronics
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Superconductor Nanostripe Single-Photon Detectors with Single-Flux Quantum Digital Logic
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Scalable Superconductor Ising Machine for Combinatorial Opti- mization Problems
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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On-Chip Control and Readout Circuits for Superconductor Ising Annealer
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Partitioning SFQ Circuits for Current Recycling with Driver-Receiver Pair Insertion
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Partitioning SFQ Circuits for Serial Biasing in Heterogeneous Cir- cuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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PhaseConnect: Automated Circuit Design for the Superconductor Phase- Based Logic
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Presented at the CLEO2024
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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qConnect: Increasing Qubit Connectivity in Quantum Computing Fabric Using Active Resonators
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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ScVMM: Vector-Matrix Multipli- cation Using Superconductor Devices
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Three-input SFQ Multiplexer
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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A Multi-Stage FPGA-Based Instrumentation Platform for Characterization and Signal Integrity Testing of Superconducting Interconnects at Cryogenic Temperatures
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
An On-Chip Trainable Neuron Circuit for SFQ-Based Spiking Neural Networks
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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AR-SFQ: Asynchronous Reset Library Using α-Cell Design
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Challenges and Unexplored
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Fast Phase Logic Family for Achieving Very Large Scale Integration in Superconductor Electronics
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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High-density superconductive logic circuits utilizing 0 and π Josephson junctions
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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qConnect: Increasing Qubit Connectivity in Quantum Computing Fabric Using Active Transmission Lines
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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SAIM: Scalable Analog Ising Machine for Solving Quadratic Binary Optimization Problems
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Scalable superconductor neuron with ternary synaptic connections for ultra-fast SNN hardware
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Superconductor logic implementation with all-jj inductor-free cell library
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Thermal Exploration of RSFQ Integrated Circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Unsupervised SFQ-Based Spiking Neural Network
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Programmable Bistable Vortex Logic for Scalable Circuit Implementation
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
qCS: quantum Circuit Studio for Optimization of Superconductor Logic Families
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Scalable Single Flux Quantum Asyn- chronous Up-Down Counter using bidirectional α-Cells
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
ScMVM: Matrix-Vector Multi- plication using Superconductor Vortex Memory
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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SuperSNN: Superconductor Spiking Neural Network Design to Fabricate
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Electrical testing of SSPD-SFQ two-photon coincidence correlator
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
A Multi-Stage FPGA-Based Instrumentation Platform for Char- acterization and Signal Integrity Testing of Superconducting Devices at Cryogenic Temperatures
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Current Recycling in Heterogenous Circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Deep Neuromorphic Networks with Su- perconducting Single Flux Quanta
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Efficient Multiplier Architecture Tailored for Superconductor Logic
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Modified Superconducting Single-Flux Quantum Two-Photon Coincidence Correlator for Single-Photon Measurements
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Observation of fractional vortices and π phases in Josephson junctions involving periodic magnetic layers
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Signal integrity simulations of Suzuki stack pulses from 4 K to CMOS circuitry at 50 K
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum-Flux-Parametron Superconducting Circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Thermal Analysis Methodology for Single Flux Quantum ICs
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Transmission Lines in VLSI Complexity Single Flux Quantum Systems
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Electrically-controlled hybrid superconductor-ferromagnet cell for high-density cryogenic memory
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Harnessing Stochasticity for Superconductive Multi-Layer Spike-Rate-Coded Neuromorphic Networks
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Inductive and Capacitive Coupling Noise in Superconductive VLSI Circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Investigation of the Critical Currents in Thin-Film MoGe Devices
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Josephson parametric oscillator based Ising machine
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Simulation and Design of Quantum Phase Slip Junction-Based Parametric Amplifiers
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Transport Properties of NbN-Cu Bilayer Superconducting Nanowires
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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DC-biased Suzuki stack circuit for Josephson- CMOS memory applications
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Design of a Superconducting Multiflux Non-Destructive Readout Memory Unit
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Design of Integrated SNSPD-RSFQ Two-Photon Coincidence Correlator with Energy Efficient Biasing Scheme
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Evidence for chiral edge modes in binary multilayers of normal and magnetic nm-thick metallic films
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
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Hybrid Nb/MoGe Josephson junctions for superconducting electronics
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Interconnect Benchmark Circuits for Single Flux Quantum Integrated Circuits
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Scalable Superconductor Neuron Structure for Ultra-High-Performance Spiking Neural Network Hardware with Ternary Synaptic Connections
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
SFQ Multi-Clock Generator
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
An Integrated Place & Route Tool for Handling SFQ Circuits Comprising Simple and Complex Multi-Stage Logic Cells
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and the intended research or engineering use.
License: [TBD] · Version: [TBD]
Waiver Required
Josephson oscillators based on amorphous superconductors
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and the intended research or engineering use.
