Research | DiscoverExpedition

Research Overview

Basics of SuperSoCC

SuperSoCC stands for Superconductive System of Cryogenic (computing) Cores. It is an essential first step toward ultimately realizing an exascale superconductive supercomputer. The DISCoVER Expedition's goal is to build a fully operational SuperSoCC, a system composed of cryogenic compute cores and superconductive memory running together to execute applications at scale. Our program will leap beyond the existing design capability of current SCE research. Our vertically integrated team will effectively combine new technologies, circuits, architecture, interfaces, and design methodologies into a critically important demonstration vehicle. Our integrated SuperSoCC solution will support a wide range of heretofore unheard-of applications.

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THRUST 01 / 05

SuperSoCC Design

Produce a SuperSoCC prototype over two design phases spanning the project duration.

PHASE 1

Exploit the limited on-chip SoC memory, standard JJ devices, and existing interface technologies in design, validate, and demonstrate a SCE system.

PHASE 2

Embark on the more aggressive SuperSoCC design and fabrication with continued innovations from our other research thrusts.

Cross-Phase Challenges — Tackle a variety of challenges across the two phases such as devices, circuits, architecture, memory, interfacing and software.

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Fig. 1 — SuperSoCC three-stage cryogenic architecture

THRUST 02 / 05

Circuits and Architecture

Demonstrate the SuperSoCC successfully.
Develop novel circuits/architectures in support of evolving superconductor technologies.
Produce design techniques that support large-scale high-complexity superconductive systems.
Solve the long term issue of superconductor memory.
Tackle the development of circuits and architectures for very large scale integration (VLSI) complexity, high-performance, ultra-low power superconductive systems.

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Fig. 2 — Superconducting logic and control architecture

THRUST 03 / 05

Devices and Materials

Create accurate models of new devices for use in ongoing CAD development.
Incorporate novel materials and device structures.
Focus on 2pJ and φ JJs to optimize performance, manufacturability, and scalability.
Develop a small, area, energy-efficient, non-volatile, fully addressable memory cell.
Demonstrate a scalable, dense RAM array with energy-efficient "Read" and "Write" operations free of a half-select problem.
Innovate multi-terminal transistor-like and nanowire-based superconductive devices primarily intended for interface circuits.

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Fig. 3 — Multi-layer superconductive memory cell stack

THRUST 04 / 05

Integration and Interfacing

Create new technologies for power and data links while considering the challenging electrical and thermo-mechanical aspects of these interfaces.
Develop specialized circuitry to transfer data across and between different temperature stages.
Apply passive integration technology to cryogenic systems.
Evaluate material properties of the interconnect and interface components at cryogenic temperatures.
Apply efficient, fast, and high-throughput active interface technology to transfer data between low temperature circuits and from low temperature circuits and multi-chip modules to system components operating at room temperature.

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Fig. 4 — Cryogenic-to-room-temperature interface stage

THRUST 05 / 05

Business and Socioeconomic Impacts

Develop and demonstrate computing systems built from superconductive electronics.
Capable of yielding ~100x improved energy efficiency compared to CMOS at ISO performance levels.
Seminal impact on climate and green environment.
Enable novel computing capabilities.
Ultra-high-performance computing.
Machine learning acceleration.
Solve hard combinatorial problems.
Broader societal impacts.
Accurate models of climate change effect.
Enhanced pharmaceutical.

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Fig. 5 — Five domains of impact radiating from the SuperSoCC platform, redrawn from the team's original diagram